An important trend in development of semiconductor technology is scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) for improving integration level and reducing manufacturing cost. However, it is well known that short channel effects arise as the size of MOSFETs decreases. As the MOSFETs are scaled down, a gate also has a reduced effective length and actually controls fewer charges in a depletion region when a gate voltage is applied. Consequently, a threshold voltage of the MOSFETs drops with a reduced channel length.
It is disclosed in “Scaling the Si MOSFET: From bulk to SOI to bulk”, Yan et al., IEEE Trans. Elect. Dev., Vol. 39, p. 1704, June, 1992, that a ground plane (i. e., a backgate being grounded) can be arranged below a buried oxide layer for suppressing short channel effects in an SOI MOSFET.
However, the above-mentioned SOI MOSFET with the back gate must be grounded or biased to a predetermined potential during operations. For this, an additional chip area is required for providing electrical contacts with the back gate, for example, to form additional vias and wirings.
Therefore, it is still desirable to provide a back gate in a MOSFET while reducing a footprint on a wafer.